library verilog;
use verilog.vl_types.all;
entity code_select_021 is
    port(
        code_021        : out    vl_logic_vector(3 downto 0);
        data0x_021      : in     vl_logic_vector(3 downto 0);
        data1x_021      : in     vl_logic_vector(3 downto 0);
        data2x_021      : in     vl_logic_vector(3 downto 0);
        data3x_021      : in     vl_logic_vector(3 downto 0);
        data4x_021      : in     vl_logic_vector(3 downto 0);
        data5x_021      : in     vl_logic_vector(3 downto 0);
        add_021         : in     vl_logic_vector(2 downto 0)
    );
end code_select_021;
